From a previous post you may remember this diagram
The seleae logic analyser did a good job of decoding this because if you can see, the variation between long and short pulses in some cases are well outside most algorithms to decode, the MLX90109 data sheet says how the built in manchester decoder will make this easy, all you have to do is check for a 50% duty cycle clock and clock the binary on the positive clock pulse.
To save you doing this I have two working circuits none of which produce anything like a 50% duty cycle, in fact the clock signal is just a mirror of the manchester data at twice the frequency. so what is going wrong?
The data sheet is very poor on this and to prove it works I’ve ordered the MLX90109 development kit, hopefully using this I should have some more positive news next time.
Of course I’m only getting snatches of times between work and sleep to do this so I am not giving it the full attention it deserves. The other option of course is to write a more fuzzy manchester decoder and ignore the built in decoder and this may be what I will do if I dont make any progress on finding the problem with the decoder.